
`timescale 1ns/100ps

module ad_data_clk #(

  parameter   SINGLE_ENDED = 0
) (
  input               rst,
  output              locked,

  input               clk_in_p,
  input               clk_in_n,
  output              clk
);

  // internal signals

  wire                clk_ibuf_s;

  // defaults

  assign locked = 1'b1;

  // instantiations

  generate
  if (SINGLE_ENDED == 1) begin
  IBUFG i_rx_clk_ibuf (
    .I (clk_in_p),
    .O (clk_ibuf_s));
  end else begin
  IBUFGDS i_rx_clk_ibuf (
    .I (clk_in_p),
    .IB (clk_in_n),
    .O (clk_ibuf_s));
  end
  endgenerate

  IBUF i_clk_gbuf (
    .I (clk_ibuf_s),
    .O (clk));

endmodule
